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More info: Writing

Tips for writing blogs

引言

两大类存储引擎：日志结构（log-structured） 的存储引擎，以及 面向页面（page-oriented） 的存储引擎（例如 B 树）。

• 日志
  一个 仅追加（append-only） 的数据文件
  写入非常快，但是搜索效率很低

Buses in Von Neumann Architecture (Unit 5.1)

3 Information flows (bus):

The Fetch-Execute Cycle (Unit 5.2)

The basic CPU loop:

Write 2 programs in Hack Machine Language:

1. a loop doing multiplication;
2. a listener for keyboard to blacken the screen.

Working with Registers and Memory (Unit 4.6)

Let’s recall

• D: data register
• A: address / data register
• M: the currently selected memory register: M = RAM[A]

Input and Output (Unit 4.5)

We will learn to use bits to manipulate the peripheral devices.

Screen Memory Map

There is a display unit (256 * 512, b/w)

The Screen Memory Map is a sequence of 16-bit values, each of which is called “a word”. Altogether we have 8k (8192), 16-bit words, because there should be this much bits (one for each pixel).

Note that the read/write operations are only 16-bit, not individual bits.

Overview (Unit 4.1)

Alan Turing raised the idea of Universality and considered the theoretical model.

This idea was turned into practice by Von Neumann, who built the first serious architecture of a general computing machine.

How the Instructions look in a computer

0100010 0011 0010

ADD R3 R2 : Add R3 to R2

​ We are going to implement 8 chips in this project.

The Chips to implement

1-Bit Register Chip

Tip: It can be built from a DFF and a multiplexor.

16-Bit Register

Tip: A little bit different wiring from the last one.

Memory Units (Unit 3.3)

Given the 1-bit register we learned in the last post, we can build more things!

The basic memory element: Register

• We use 16-bit word width to keep generality

Sequential Logic (Unit 3.1)

In this unit we introduce the issue of time into the system, since we didn’t have the notion of change before. To simplify the concept, we divide time into atomic pieces, which is clock.

Clock (Integer Time Unit)

Clock can be viewed as an oscillator at a certain fixed rate, of which each cycle is treated as a time unit, like time 0, time 1 and so on.

The signals are viewed as a indivisible thing as if nothing changes within each time unit. As a input signal is renewed every cycle, the output signal instantaneously follows (几乎同时).

You may wonder if this is real. Indeed, there may be delay in physical electrical signals. But, we can think it as a way that the voltage change (the grey area in the screenshot below) happens between cycles, while luckily, the cycles are a little bit wider than this instability. So, it is safe to ignore it and focus on the end of each time unit.